RTL Design
Specializing in microarchitecture development, RTL coding, LINT checks, CDC analysis, and synthesis optimization.synthesis flow, functional verification, and formal verification.
UVM-Based Verification
Skilled in Verilog, SystemVerilog, and UVM methodologies, with hands-on experience in AMBA protocols, testplan creation, testbench development, functional coverage analysis, and debugging.
RISC-V Verification
Expertise in verifying RISC-V architectures, including instruction formats, writing custom assembly testcases, architectural compliance, and algorithmic validation.
Formal Verification
Proficient in assertion-based verification with a focus on checker implementation, convergence analysis, bug hunting, coverage closure, and formal signoff.
